EPROM write speed

[okto]

I pulled apart one of my Datapaks to see what chip it contained, and what it's got is a 250ns non-CMOS 27256, which is astoundingly slow and also eats power compared to a CMOS part.

What I'm wondering is whether the slow write speeds to Datapaks are due to the slow cycle times, or if it's another issue, and if a faster part would speed up those writes. 150ns 27c256en are just laying around the place, and you can even find a 120ns part every once in a while.

Does anyone have the skinny on this?

[amenjet]

I pulled apart one of my Datapaks to see what chip it contained, and what it's got is a 250ns non-CMOS 27256, which is astoundingly slow and also eats power compared to a CMOS part.

What I'm wondering is whether the slow write speeds to Datapaks are due to the slow cycle times, or if it's another issue, and if a faster part would speed up those writes. 150ns 27c256en are just laying around the place, and you can even find a 120ns part every once in a while.

Does anyone have the skinny on this?

The 250ns access time is for a read cycle. It's fast enough to allow the device to operate on a bus, for instance. Writing EPROMs is very much slower, something around 50ms. Sometimes a higher voltage is needed as well. The datapack is powered down between accesses, so doesn't take a huge amount of power.

Andrew

[Martin]

Again give it up for Jaaps excellent page on datapaks and the like (here).

You can't take the 'P' mark on the pack label as gospel anymore as people (me included) swap the cases and the 'inners' when UV formatting them... Best to put your glasses on and look for the C in the chip name/number..

Martin

[amenjet]

Again give it up for Jaaps excellent page on datapaks and the like (here).

You can't take the 'P' mark on the pack label as gospel anymore as people (me included) swap the cases and the 'inners' when UV formatting them... Best to put your glasses on and look for the C in the chip name/number..

Martin

I thought the P stood for Paged''? Some people have swapped the links on datapacks to make then linear or paged so that messes things up too.

Andrew

[okto]

What's the difference between a paged vs unpaged pak?

[amenjet]

What's the difference between a paged vs unpaged pak?

The addressing on datapacks is serial. A clock line clocks a counter and the outputs from that counter are the address lines to the memory device(s). This is done to reduce the number of signals needed to be on the datapack connector.
The basic counter is quite small (A1 to A7, A0 is the SCLK line) and if it had been extended to larger packs would have required a large number of pulses to get the addresses needed. This would have impacted access time. So, a second counter is added (a page counter) that adds some address lines above the first counter. It's like a second 'digit'. You can clock that counter and it represents chunks of 256 addresses. You therefore have to clock SCLK less times in order to access data further up the address range of the memory devices.

Paging works up to 128K or so, then access time slows down again and for the very large packs you have a 'segment' register. That isn't a counter, rather it is a latch that is written to using the data bus That allows segments of 128K or so (these sizes may not be correct, I'm doing this from memory) that can be accessed quickly.

So, for small packs like a 32K RAM pack you may have just a counter, for the larger packs like the 256K RAM pack(*) you have two counters and a latch. The 512K flash pack(*) has two counters and a latch and also splits the address space across two devices.

This is all described in the technical manual if you want the details.
Data lines are parallel.

(*) The packs that I did, anyway, others may have a different arrangement.

Andrew

[okto]

Clever design. Is there any speed hit incurred by paging?

[amenjet]

Clever design. Is there any speed hit incurred by paging?

No, not really, when compared to the alternative of a large counter and lots of clock pulses.

Andrew