BJT Comms Link for USB

This special section for all the COMMS LINK and communications issues
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Joined: Wed Jan 04, 2023 7:51 pm

BJT Comms Link for USB

Post by MartinP »

Here’s my BJT Comms Link, which I’ve been meaning to re-post since the Forum moved to its new home. I built this during April 2022 to explore the basic essentials of serial comms on the Organiser, and I wanted to see if it was possible to build a minimal USB comms link using only bipolar junction transistors (BJTs), plus a few resistors. I used it successfully to transfer files to and from the Organiser using the Psion Protocol.

The circuit consists of two buffers for the serial data lines (a buffer copies a signal to avoid a direct connection). The serial input buffer is gated to ensure that an incoming signal is only allowed on to the Psion’s data line when it’s safe to do so. The serial output buffer isn’t gated.

Because the circuit doesn’t have its own ROM (to be minimal), it requires the comms link ROM to be written to a datapak and placed in one of the datapak slots.

To convert between the Organiser's TTL level (5V) serial signals and USB, I used an FTDI UART to USB adaptor; these FTDI modules come in 5V versions, so no level shifting was required. Also, there’s no need for RS232 voltage levels if connecting to a modern PC with USB.

I built the circuit on a breadboard, and for connections to the top slot, I soldered wires to a standard Psion power adapter board, see below.
BJT Comms link buffer_w.jpg
Just a word of caution, there’s a potential risk of damage to the Organiser if wires at the top slot are connected to the wrong places, so only do this type of thing if you are confident.

Without a ROM at the top slot, the only thing the logic circuit needs to do is control when it’s safe to allow serial input onto the data bus. This occurs when the slot is selected and ROM output is not enabled.

A logic diagram of the standard comms link buffer-enable state is shown below. When the slot select (SS_B) is enabled (low) and ROM output (OE_B) is disabled (high), the NAND gate output goes low, giving a buffer enable (BUFFER_OE_B).
NAND logic.PNG
The BJT circuit is shown below. For the serial input (Tx to P-Rx, where Tx is the USB's transmission data and P-Rx is the Psion’s incoming receive data), the buffer enable logic uses NPN transistors (Q1-Q4). Q1 is an inverter and Q4 provides an extra (3rd) input to the NAND for the incoming Tx (Tx is normally high and pulses low during a signal). The state when all NAND inputs are high will send its output low and pull the base of the PNP (Q5) low, this takes the P-Rx level high (so will be the same as Tx). Also, the LED is lit when the NAND output (collector of Q2) is low. When the NAND output is high, the PNP is off and its collector has a high impedance, so the P-Rx (D3) data line is unaffected or will be pulled low by the Psion's internal pull-down resistor.
The serial output buffer (P-Tx to Rx) is even simpler; it protects the Psion's outgoing serial P-Tx (D4) signal with two inverters in series (Q6-Q7). To add some enable logic, like for the serial input, would require more transistors and isn’t essential because this is an outgoing signal. However, the D4 signal appears at the output all the time, even when the data bus is used for other things, this means the USB will receive garbage at that time, but the Psion Protocol's packet method will filter out garbage very effectively. Also, if a terminal connection is required, this could just be disconnected when it's not in use.

The BJT circuit uses up to about 20 mA, so is powered from the USB 5V because I didn’t want to drain the Organiser battery.
After building this, I moved on to using a circuit with two CMOS logic chips: a NAND and a tri-state buffer (the USB-datapak-CommsLink viewtopic.php?t=62). That circuit does the job better, and is also quite a minimal DIY solution.
Martin P.
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